A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology
نویسندگان
چکیده
A novice advanced architecture of 8-bit analog to digital converter is introduced and analyzed in this work. The structure proposed ADC based on the sub-ranging which a 4-bit resolution flash-ADC utilized. designed by employing comparator equipped with common mode current feedback gain boosting technique (CMFD-GB) residue amplifier. 8 bits can achieve speed 140 megasamples per second. at 10 MHz sampling frequency. DNL INL values design are -0.94/1.22 -1.19/1.19 respectively. dissipates power 1.24 mW conversion 0.98 ns. magnitude SFDR SNR from simulations Nyquist input 39.77 35.62 decibel Simulations performed SPICE tool 90 nm CMOS technology. comparison shows better performance for other architectures regarding speed, consumption.
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ژورنال
عنوان ژورنال: International Journal of Electronics and Telecommunications
سال: 2023
ISSN: ['2300-1933', '2081-8491']
DOI: https://doi.org/10.24425/ijet.2021.135987